Duty cycle detecting circuit for pulse width modulation

ABSTRACT

A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a duty cycle detecting circuit forpulse width modulation (PWM), and more particularly to a detectingcircuit that samples a PWM signal based on a clock frequency andcalculates the duty cycle of the pulse width modulation signal based onthe sampling results.

2. Description of the Related Art

Pulse Width Modulation (PWM) has been used extensively in electroniccircuits including motor control circuits and power supply devices. Ingeneral, a pulse signal with a fixed frequency is used for controllingthe ON and OFF states of a transistor. In a pulse width modulationsystem, a change of pulse width is used for determining the timeinterval of being active or cut-off for the transistor to achieve thecontrol effect. In other words, the duty cycle of the PWM signalindicates a proportion of the active time (or high electric potential)of the pulse signal and plays an important role in the pulse widthmodulation system.

However, the duty cycle is very sensitive to many factors including anoperating frequency, an operating temperature, a power voltage, and acircuit design. Therefore, it is an important subject to detect anactual duty cycle of a pulse signal in a pulse width modulation systemunder different operating conditions.

SUMMARY OF THE INVENTION

To achieve the foregoing objective, the present invention provides aduty cycle detecting circuit for pulse width modulation that is appliedfor detecting a duty cycle of a PWM signal, and the duty cycle detectingcircuit comprises: a clock generating circuit for generating a clocksignal; a sampling circuit for receiving the PWM signal and the clocksignal and sampling the PWM signal based on the clock signal to generatea sampling signal; and a calculation circuit for calculating the dutycycle of the PWM signal based on the sampling signal.

In the duty cycle detecting circuit for pulse width modulation, thesampling signal includes a high electric potential state and a lowelectric potential state. The calculation circuit accumulates thesampling signal as a count of high electric potential states and a totalnumber of times of sampling to obtain a count of high electric potentialstates and a total number of times of sampling respectively, and dividesthe count of high electric potential states by the total number of timesof sampling to obtain the duty cycle.

In the duty cycle detecting circuit for pulse width modulation, thecalculation circuit accumulates the sampling signal as a count of highelectric potential states and the sampling signal as a count of lowelectric potential states to obtain a count of high electric potentialstates and a count of low electric potential states respectively, anddivides the count of high electric potential states by the sum of thecount of high electric potential states and the count of low electricpotential states to obtain the duty cycle.

In the duty cycle detecting circuit for pulse width modulation, theclock generating circuit is an oscillator, and the sampling circuit is aflip-flop. The calculation circuit comprises a microprocessor unit forprocessing an operation required for calculating the duty cycle, and amemory unit for storing a computer code required for calculating theduty cycle.

In the duty cycle detecting circuit for pulse width modulation, thecalculation circuit further comprises a counter for receiving thesampling signal, and accumulating the sampling signal as a count of highelectric potential states and the sampling signal as a count of lowelectric potential states to obtain a count of high electric potentialstates and a count of low electric potential states respectively. Thecalculation circuit further includes a division circuit for dividing thecount of high electric potential states by the sum of the count of highelectric potential states and the count of low electric potential statesto obtain the duty cycle. The calculation circuit further includes areset circuit for resetting the counter after a predetermined number oftimes of sampling, so that the counter restarts accumulating the countof high electric potential states and the count of low electricpotential states again.

In the duty cycle detecting circuit for pulse width modulation, thecalculation circuit includes a counter for receiving the samplingsignal, and accumulating the sampling signal as a count of high electricpotential states and a number of times of sampling to obtain a count ofhigh electric potential states and a total number of times of samplingrespectively. The calculation circuit further includes a divisioncircuit for dividing the count of high electric potential states by thetotal number of times of sampling. The calculation circuit furtherincludes a reset circuit for resetting the counter after a predeterminednumber of times of sampling, so that the counter restarts accumulatingthe count of high electric potential states and the count of lowelectric potential states again.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a duty cycle detecting circuit forpulse width modulation in accordance with the present invention;

FIG. 2 illustrates a duty cycle detecting circuit for pulse widthmodulation in accordance with a first preferred embodiment of thepresent invention;

FIG. 3 illustrates a duty cycle detecting circuit for pulse widthmodulation in accordance with a second preferred embodiment of thepresent invention; and

FIG. 4 illustrates a relation of a PWM signal, a clock signal and asampling signal in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To make it easier for our examiner to understand the objective of theinvention, its structure, innovative features, and performance, we usepreferred embodiments together with the attached drawings for thedetailed description of the invention.

Referring to FIG. 1 for a block diagram 10 of a duty cycle detectingcircuit for pulse width modulation in accordance with the presentinvention, the duty cycle detecting circuit is applied for detecting aduty cycle of a PWM signal, and the duty cycle detecting circuitcomprises: a clock generating circuit 11 for generating a clock signal;a sampling circuit 13 for receiving the PWM signal and the clock signal,and sampling the PWM signal based on the clock signal to generate asampling signal; and a calculation circuit 15 for calculating the dutycycle of the PWM signal based on the sampling signal. The higher thefrequency of the clock signal, the higher is the sampling frequency. Thehigher the sampling frequency, the higher is the accuracy of thedetecting result. The frequency of a clock signal can be selected basedon the frequency of the PWM signal. For example, a clock equals to tentimes of the frequency of the pulse width modulation signal as thefrequency of the clock signal.

In the duty cycle detecting circuit for pulse width modulation as shownin FIG. 4, the sampling signal includes a high electric potential stateand a low electric potential state. In a preferred embodiment, thecalculation circuit accumulates the sampling signal as a count of highelectric potential states and a total number of times of sampling toobtain a count of high electric potential states and a total number oftimes of sampling respectively and divides the count of high electricpotential states by the total number of times of sampling to obtain theduty cycle.

In the duty cycle detecting circuit for pulse width modulation inaccordance with another preferred embodiment, the calculation circuitaccumulates the sampling signal as a count of high electric potentialstates and the sampling signal as a count of low electric potentialstates to obtain a count of high electric potential states and a countof low electric potential states respectively, and dividing the count ofhigh electric potential states by the sum of the count of high electricpotential states and the count of low electric potential states toobtain the duty cycle. When the sampling is performed, the cycle of asingle PWM signal is used as a unit time for the sampling to obtain theduty cycle of the single PWM signal; or the cycle of several PWM signalsis used as a unit time for the sampling to obtain an average duty cycle.

Referring to FIG. 2 for a duty cycle detecting circuit for pulse widthmodulation in accordance with a first preferred embodiment 20, the clockgenerating circuit is an oscillator 21; the calculation circuit 25comprises a microprocessor unit 251, for processing the operationrequired for calculating the duty cycle; and a memory unit 252, forstoring a computer code required for calculating the duty cycle. Thecomputer code drives the microprocessor unit 251 to accumulate thesampling signal as a count of high electric potential states and a totalnumber of times of sampling to obtain a count of high electric potentialstates and a total number of times of sampling respectively, anddividing the count of high electric potential states by the total numberof times of sampling to obtain the duty cycle, or accumulating thesampling signal as a count of high electric potential states and thesampling signal as a count of low electric potential states to obtain acount of high electric potential states and a count of low electricpotential states respectively, and dividing the count of high electricpotential states by the sum of the count of high electric potentialstates and the count of low electric potential states to obtain the dutycycle. When the sampling is performed, the cycle of the single PWMsignal is used as a unit time for the sampling to obtain the duty cycleof the single PWM signal; or the cycle of several PWM signals is used asa unit time for the sample to obtain an average duty cycle.

Referring to FIG. 3 for a duty cycle detecting circuit for pulse widthmodulation in accordance with a second preferred embodiment 30, theclock generating circuit is an oscillator 31; the sampling circuit is anflip-flop 33; and the calculation circuit 35 comprises a counter 351 forreceiving the sampling signal, and accumulating the sampling signal as scount of high electric potential states and the sampling signal as acount of low electric potential states to obtain a count of highelectric potential states and a count of low electric potential statesrespectively. The calculation circuit 35 further includes a divider 355for dividing the count of high electric potential states by the sum ofthe count of high electric potential states and the count of lowelectric potential states to obtain the duty cycle. The calculationcircuit 35 further includes a reset circuit 353 for resetting thecounter 351 after a predetermined number of times of sampling, so thatthe counter 351 starts accumulating the count of high electric potentialstates and the count of low electric potential states again.

In a duty cycle detecting circuit for pulse width modulation inaccordance with a second embodiment, the counter 351 accumulates thesampling signal as a count of high electric potential states and a totalnumber of times of sampling to obtain a count of high electric potentialstates and a total number of times of sampling respectively. The divider355 divides the count of high electric potential states by the totalnumber of times of sampling to obtain the duty cycle.

While the duty cycle detecting circuit for pulse width modulation inaccordance with the invention has been described by means of specificembodiments, numerous modifications and variations could be made theretoby those skilled in the art without departing from the scope and spiritof the invention set forth in the claims.

1. A duty cycle detecting circuit for pulse width modulation, appliedfor detecting a duty cycle of a PWM signal, comprising: a clockgenerating circuit, for generating a clock signal; a sampling circuit,for receiving the PWM signal and the clock signal, and sampling the PWMsignal based on the clock signal to generate a sampling signal; and acalculation circuit, for calculating the duty cycle of the PWM signalbased on the sampling signal.
 2. The duty cycle detecting circuit forpulse width modulation of claim 1, wherein the sampling signal comprisesa high electric potential state and a low electric potential state. 3.The duty cycle detecting circuit for pulse width modulation of claim 2,wherein the calculation circuit accumulates the sampling signal into acount of high electric potential states and a total number of times ofsampling to obtain a count of high electric potential states and a totalnumber of times of sampling respectively.
 4. The duty cycle detectingcircuit for pulse width modulation of claim 3, wherein the calculationcircuit divides the count of high electric potential states by the totalnumber of times of sampling to obtain the duty cycle.
 5. The duty cycledetecting circuit for pulse width modulation of claim 2, wherein thecalculation circuit accumulates the sampling signal as a count of highelectric potential states and the sampling signal as a count of lowelectric potential states to obtain a count of high electric potentialstates and a count of low electric potential states respectively.
 6. Theduty cycle detecting circuit for pulse width modulation of claim 5,wherein the calculation circuit divides the count of high electricpotential states by a sum of the count of high electric potential statesand the count of low electric potential states to obtain the duty cycle.7. The duty cycle detecting circuit for pulse width modulation of claim1, wherein the clock generating circuit is an oscillator.
 8. The dutycycle detecting circuit for pulse width modulation of claim 1, whereinthe calculation circuit comprises: a microprocessor unit, for processingan operation required to calculate the duty cycle; and a memory unit,for storing a computer code required to calculate the duty cycle.
 9. Theduty cycle detecting circuit for pulse width modulation of claim 1,wherein the sampling circuit is a flip-flop.
 10. The duty cycledetecting circuit for pulse width modulation of claim 9, wherein thecalculation circuit comprises a counter for receiving the samplingsignal, and accumulating the sampling signal as a count of high electricpotential states and the sampling signal as a count of low electricpotential state to obtain a count of high electric potential states anda count of low electric potential states respectively.
 11. The dutycycle detecting circuit for pulse width modulation of claim 10, whereinthe calculation circuit further comprises a divider for dividing thecount of high electric potential states by a sum of the count of highelectric potential states and the count of low electric potential statesto obtain the duty cycle.
 12. The duty cycle detecting circuit for pulsewidth modulation of claim 10 or 11, wherein the calculation circuitfurther comprises a reset circuit for resetting the counter after apredetermined number of times of sampling, so that the counter restartsaccumulating the count of high electric potential states and the countof low electric potential states again.
 13. The duty cycle detectingcircuit for pulse width modulation of claim 9, wherein the calculationcircuit further includes a counter for receiving the sampling signal,and accumulating the sampling signal as a count of high electricpotential states and a total number of times of sampling to obtain acount of high electric potential states and a total number of times ofsampling respectively.
 14. The duty cycle detecting circuit for pulsewidth modulation of claim 13, wherein the calculation circuit furthercomprises a divider for dividing the count of high electric potentialstates by the total number of times of sampling to obtain the dutycycle.
 15. The duty cycle detecting circuit for pulse width modulationof claim 13 or 14, wherein the calculation circuit further comprises areset circuit for resetting the counter after a predetermined number oftimes of sampling, so that the counter restarts accumulating the countof high electric potential states and the count of low electricpotential states again.